TSV Filling, Taiko Backgrinding & BSPDN Mechanics

01Hardware Architecture & Process Train

Executing high-yield Through-Silicon Via (TSV) fabrication, extreme wafer thinning, and Backside Power Delivery Networks (BSPDN) requires a multi-equipment unit process train:

1. High-Aspect-Ratio Etch Module: Deep Reactive Ion Etching (DRIE) Bosch process tools for etching 10:1 to 20:1 aspect ratio via holes.
2. Vacuum Deposition & Electroplating Suite: SACVD/PECVD for conformal $Si{O}_2/SiN$ isolation liners, iPVD for Ti/Cu seed, and specialized periodic pulse reverse (PPR) electroplating cells.
3. Temporary Wafer Bonding / Debonding System: High-precision adhesive spin-coaters and thermal/photonic debonding tools.
4. Precision Backgrinding & Taiko Tools: Multi-spindle coarse/fine diamond-wheel grinding systems and chemical mechanical polishing (CMP) tools for TSV reveal.

02High-Aspect-Ratio TSV Filling Kinetics

Etching and filling a TSV ($10\mu \text{m}$ diameter, $100\mu \text{m}$ depth, 10:1 aspect ratio) presents extreme mass-transfer challenges compared to shallow BEOL trenches:

A. Conformal Insulation Liner & Barrier Deposition

• Dielectric Isolation Liner ($200-500\text{ nm}$): Deposited via Sub-Atmospheric CVD (SACVD) using $TEOS/O_3$ or Low-Temperature PECVD ($SiN/Si{O}_2$) to prevent electrical leakage into the bulk silicon substrate.
• Diffusion Barrier & Seed ($100-300\text{ nm}$): Ionized PVD (iPVD) sputtering of Titanium (Ti) or Tantalum (Ta) barrier and Copper (Cu) seed layer. High RF chuck bias is applied to drive metal ions deep into the $100\mu \text{m}$ cavity without pinching off the top entrance.

B. Specialized ECP Pulse Plating

Standard ECP DC current causes rapid top-opening pinch-off, leaving huge voids inside deep TSVs. To prevent this, Periodic Pulse Reverse (PPR) electroplating is employed:

• Forward Pulse ($I_{\text{forward}}$): Plating current applied to deposit copper along the via walls.
• Reverse Pulse ($I_{\text{reverse}}$): Brief high-current anodic pulse that preferentially dissolves copper build-up from top entrance overhangs where electric fields concentrate.
• Organic Additive Dynamics: Extremely high concentrations of slow-diffusing Suppressors seal top openings, while strong Accelerators drive bottom-up growth.

03Wafer Thinning: Standard Carrier vs. DISCO Taiko Process

Thinning a $300\text{ mm}$ silicon wafer from $775\mu \text{m}$ down to $<50\mu \text{m}$ removes mechanical rigidity, causing extreme wafer warp and stress-induced fracturing. Two handling approaches are used:

A. Standard Temporary Carrier Bonding Flow

1. Active wafer front-side is spin-coated with a thermoplastic high-temperature adhesive ($15-30\mu \text{m}$).
2. Bonded under vacuum and heat ($200^{\circ }\text{C}$) to a rigid glass or silicon carrier wafer ($725\mu \text{m}$).
3. Wafer thinned completely across its entire diameter via coarse grinding (#320-360 diamond mesh) followed by fine polishing (#2000-20000 mesh).
4. After backside processing, adhesive is debonded via laser ablation ($355\text{ nm}$ UV laser through glass carrier) or thermal slide debonding.

B. The DISCO Taiko Process

In the Taiko process, backgrinding leaves a $3-5\text{ mm}$ thick rigid silicon ring around the outer edge of the wafer, thinning only the inner central region.

• Advantages: The thick outer ring maintains structural integrity, drastically reducing wafer warpage without requiring a temporary carrier wafer. Enables direct handling in standard fab cassettes, wet cleaning benches, and high-temperature backside anneal furnaces up to $400^{\circ }\text{C}$.

04Backside CMP & TSV Reveal Sequence

To expose buried copper TSVs from the backside without smearing copper metal across the silicon substrate:

1. Coarse/Fine Backgrinding: Stops approximately $5-10\mu \text{m}$ above the TSV copper tips.
2. Silicon Dry/Wet Etching: Selective SF6 plasma or TMAH wet etch selectively recedes the silicon substrate, leaving copper TSV tips protruding $2-3\mu \text{m}$ above the surface.
3. Backside Passivation Deposition: Low-temperature PECVD $Si{O}_2/SiN$ dielectric deposited over the exposed tips.
4. Touch-up CMP Reveal: Chemical mechanical polishing removes dielectric over the TSV tips, leaving perfectly flush, isolated copper contacts ready for micro-bumping or hybrid bonding.

05Summary & Key Takeaways

• DRIE Bosch Process etches smooth, high-aspect-ratio (> 10:1) TSV cavities.
• PPR Electroplating combined with specialized additives achieves void-free TSV copper filling by periodically dissolving top pinch-off overhangs.
• Temporary Wafer Bonding supports thinned wafers down to $5\mu \text{m}$ using laser-debondable thermoplastic adhesives.
• Taiko Backgrinding retains a $3-5\text{ mm}$ outer silicon ring to prevent warpage without requiring carrier substrates.
• Controlled TSV Reveal combines selective silicon recessed etching, PECVD passivation, and touch-up CMP.

→Prerequisites & continue reading

Prerequisites: ["p08-t8.2-t1-tsv-wafer-thinning-bspdn-fundamentals.md"]

Also in Topic 8.2, TSVs, Wafer Thinning & Backside Power:

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