Silicon University / Track A / Pillar 08 · BEOL & Packaging
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TSVs, Wafer Thinning & Backside Power
Step 23 of 24 · BEOL Metallization, Advanced 2.5D/3D Packaging & Heterogeneous Integration · three tiers, 57 min total.
Packaging phase
Topic 8.2
3 articles
Tier 1 · Core FundamentalsThrough-Silicon Vias (TSV), Wafer Thinning & BSPDN: Core Fundamentals
Introduces Through-Silicon Vias (TSVs)—microscopic vertical copper pillars etched directly through silicon wafers—enabling high-speed 3D stacking of memory (HBM) and logi…
Tier 2 · Equipment & KinematicsTSV Filling, Taiko Backgrinding & BSPDN Mechanics
Mechanical design of temporary carrier wafer bonding tools using high-temperature adhesives, ultra-precision wheel back-grinders thinning wafers down to 30µm, edge bead t…
Tier 3 · Deep-Dive & Yield EngineeringThermomechanical Stress, TSV Extrusion & Buried Power Rails Physics
Finite Element Analysis (FEA) of thermal expansion mismatch (CTE) between Cu and Si causing copper extrusion (pop-out), sub-micron insulator liner step coverage, and Back…