Silicon UniversitySEMICONDUCTOR MANUFACTURING About the project

Fab Flow

101 Quartzite
102 Ingot
103 Wafering
104 FEOL
105 BEOL
106 Packaging

Silicon University / Track B matrix

08

BEOL Metallization, Advanced 2.5D/3D Packaging & Heterogeneous Integration

Pillar 08 of 8, three topics, nine articles: beol metallization, dual damascene & low-k, tsvs, wafer thinning & backside power, hybrid bonding & chiplet integration.

3 topics9 articles 3 tiers

Topic 8.1 · BEOL Metallization, Dual Damascene & Low-k

3 articles · 3 tiers · Track A step 22

Tier 1BEOL Metallization, Dual-Damascene & Low-k Dielectrics: Core Fundamentals12 min

Tier 2Copper Electroplating, PVD Barrier & Pore Sealing Mechanics18 min

Tier 3Electromigration, RC Delay & Ultra-Low-k Physics25 min

Topic 8.2 · TSVs, Wafer Thinning & Backside Power

3 articles · 3 tiers · Track A step 23

Tier 1Through-Silicon Vias (TSV), Wafer Thinning & BSPDN: Core Fundamentals12 min

Tier 2TSV Filling, Taiko Backgrinding & BSPDN Mechanics20 min

Tier 3Thermomechanical Stress, TSV Extrusion & Buried Power Rails Physics25 min

Topic 8.3 · Hybrid Bonding & Chiplet Integration

3 articles · 3 tiers · Track A step 24

Tier 1Direct Copper Hybrid Bonding & Chiplet Integration: Core Fundamentals12 min

Tier 2Cu-Cu Hybrid Bonding Cleanliness, Equipment & Die-to-Wafer Mechanics20 min

Tier 3Surface Activation, Dislocation Interdiffusion & Thermal Physics in Hybrid Bonding25 min

Engineer in a cleanroom suit beside an overhead rail wafer transport system carrying wafer carriers across the fab — FABOverhead rail wafer transport on the fab floor