Dishing & Erosion Tribochemical Models: Sub-10nm Interconnect Topography

01Executive Summary

As back-end-of-line (BEOL) interconnect dimensions scale into sub-10nm logic nodes, copper line dishing and dielectric erosion become primary limiters of device yield and signal integrity. Uncontrolled topography variations cause cross-sectional area reductions that spike wire resistance (R), increase inter-line capacitive coupling (C), and induce disastrous electro-migration failures. This advanced monograph presents analytical tribochemical models for dishing and erosion, pad flexure beam dynamics, pattern density dependence, and advanced mitigation strategies.

02Topographical Defect Definitions & Electrical Impact

In copper Damascene CMP, the co-polishing of materials with radically different mechanical hardnesses ( $H_{Cu} \approx 1 GPa$ vs. $H_{ILD} \approx 8 - 10 GPa$ ) leads to two distinct topographical defects:

Copper Dishing ( $d_{d i s h}$ ): The vertical recession of the copper surface below the adjacent dielectric boundary in isolated wide lines.
Dielectric Erosion ( $e_{ero}$ ): The overall vertical loss of the dielectric oxide matrix within dense arrays of narrow copper lines.

Dishing And Erosion Topography Definitions:Schematic · source diagram

Electrical Resistance & RC Delay Penalty

For a copper wire of nominal width w, height h, and length L, dishing reduces the effective conductor cross-sectional area by $Δ A \approx w \cdot d_{d i s h}$ . The resulting electrical line resistance R increases non-linearly:

R = ρ_{Cu} \cdot \frac{L}{w \cdot ( h - d _{d i s h} )}

In sub-10nm nodes where wire height $h < 30 nm$ , a dishing depth of just $d_{d i s h} = 5 nm$ causes a $> 20%$ spike in line resistance, severely degrading clock frequencies and inducing electromigration voiding.

03Analytical Tribochemical Models for Dishing

Dishing occurs because the elastic polyurethane polishing pad flexes under applied down-force pressure and dips into soft copper trenches.

2.1 Pad Bending Beam Dynamics

Modeling the polishing pad as an elastic beam with Young's modulus $E_{p}$ and flexural rigidity $D_{p} = E_{p} t_{p}^{3} /12 (1 - ν_{p}^{2})$ , the pad deflection y(x) spanning a copper trench of width w under local pressure $P_{0}$ is governed by the bi-harmonic bending equation:

D_{p} \cdot \frac{d ^{4} y}{d x ^{4}} + k_{s} \cdot y = P_{0}

Solving boundary conditions at trench edges ( $x = \pm w /2$ ) yields the maximum central dishing depth $d_{d i s h, ma x}$ :

d_{d i s h, ma x} = \frac{P _{0}}{k _{s}} \cdot (1 - \frac{cosh ( λ w /2 ) cos ( λ w /2 )}{cosh ^{2} ( λ w /2 ) + sinh ^{2} ( λ w /2 )})

Where $λ = (k_{s} /4 D_{p})^{1/4}$ represents the characteristic structural decay length of the pad, and $k_{s}$ is the elastic foundation modulus.

Key Physical Scaling Laws

Line Width Dependence (w): Dishing increases exponentially with trench width w. For $w ≪ 1/ λ$ , dishing is negligible; for wide power rails ( $w > 10 μ m$ ), dishing saturates at its maximum limits.
Over-Polish Time Sensitivity ( $t_{o p}$ ): Dishing scales linearly with over-polish time:

d_{d i s h} (t) = d_{d i s h, 0} + (MRR_{Cu} - MRR_{ILD}) \cdot t_{o p}

04Dielectric Erosion Dynamics & Pattern Density Effects

Erosion occurs because dense arrays of copper lines reduce the local areal fraction of hard dielectric, increasing the effective contact pressure $P_{e ff}$ on the remaining dielectric features.

Local Pressure Redistribution Model

If a die region has a local copper pattern density $α$ (where $α = Area_{Cu} / Area_{Total}$ ), the local effective pressure $P_{e ff}$ exerted by the pad onto the dielectric asperities during Step 2 CMP is elevated:

P_{e ff, I L D} = \frac{P _{n o mina l}}{1 - α}

Pattern Density Pressure Concentration:Schematic · source diagram

As pattern density $α \to 1.0$ , the effective pressure on the remaining dielectric structures spikes dramatically, driving rapid dielectric loss ( $e_{ero}$ ) and localized array sinking.

05Advanced Dishing & Erosion Mitigation Matrix

Mitigation Strategy	Physical Mechanism	Technical Implementation	Trade-Off
Fixed-Abrasive CMP Pads	Abrasives embedded in rigid resin posts prevent pad flexure into trenches	Ceria/Silica particles bonded to hard composite pad matrix	Higher wafer defectivity & micro-scratching
Metal Dummy Fill Insertion	Breaks up wide dielectric fields and wide Cu rails to unify local pattern density $α \approx 0.5$	Automated EDA layout dummy metal insertion routines	Increases inter-line parasitic capacitance
High-Fixed-Modulus Polyurethane Pads	Elevates pad flexural rigidity $D_{p}$ , suppressing pad dipping	Hard sub-pads with high elastic modulus ( $E_{p} > 500 MPa$ )	Degrades wafer-scale macro-uniformity (WIWNU)
High-Selectivity Barrier Slurries	Chemical inhibition limits chemical Cu dissolution during Step 2 over-polish	Self-assembled inhibitor monolayers (BTA/Triazoles)	Tightens process window for complete barrier removal

→Prerequisites & continue reading

Prerequisites: ["p03-t3.2-t2-barrier-slurry-chemistry-galvanic-corrosion"]

Also in Topic 3.2, Copper Damascene & Barrier CMP:

Tier 1 · Copper Damascene & Barrier CMP Fundamentals: Multi-S…Tier 2 · Barrier Slurry Chemistry & Galvanic Corrosion: Elect…