Atomic Layer Deposition (ALD) & High-k Metal Gate (HKMG) Fundamentals

01The High-k Concept & Equivalent Oxide Thickness (EOT)

The capacitance (C) of a planar gate capacitor is given by:

C = \frac{κ ε _{0} A}{t _{d}}

Where:

$κ$ (or k) is the relative dielectric constant ( $κ_{S i O_{2}} \approx 3.9$ ).
$ε_{0}$ is the vacuum permittivity ( $8.854 \times 1 0^{- 12} F/m$ ).
A is the gate area.
$t_{d}$ is the physical thickness of the dielectric.

By replacing $S i O_{2}$ with a High-k dielectric like Hafnium Oxide ( $H f O_{2}$ , $κ \approx 20 - 25$ ), process engineers can increase the physical film thickness $t_{d}$ by a factor of 5 to 6 while maintaining the exact same capacitive gate drive control!

The metric used to compare high-k films against $S i O_{2}$ is Equivalent Oxide Thickness (EOT):

EOT = t_{high-k} (\frac{κ _{S i O_{2}}}{κ _{high-k}})

A $2.5 nm$ thick $H f O_{2}$ layer ( $κ = 20$ ) yields an EOT of only $0.48 nm$ , providing massive gate drive current while suppressing quantum tunneling leakage by several orders of magnitude.

02Why Metal Gates Replaced Polysilicon

When high-k dielectrics were initially placed under traditional polysilicon gate electrodes, two major failure modes occurred:

Polysilicon Depletion: A charge-depleted layer formed at the poly-Si/dielectric interface, adding $0.4 - 0.5 nm$ of unwanted parasitic EOT.
Fermi-Level Pinning: Chemical reactions between poly-Si and $H f O_{2}$ pinned the threshold voltage ( $V_{t h}$ ), making transistors difficult to turn off.

Replacing polysilicon with Metal Gates (such as Titanium Nitride $TiN$ or Tantalum Nitride $TaN$ ) eliminated polysilicon depletion completely and enabled precise work function engineering for NMOS and PMOS devices.

03Principles of Atomic Layer Deposition (ALD)

Because high-k films must be deposited uniformly inside deep 3D FinFET and GAA nanosheet structures with sub-nanometer thickness control, physical vapor deposition (PVD) and chemical vapor deposition (CVD) are inadequate.

Atomic Layer Deposition (ALD) is a specialized form of CVD based on self-limiting sequential surface reactions:

Typical Ald Cycle (Hfo2)Schematic · source diagram

Each 4-step ALD cycle deposits precisely one atomic monolayer (~ $0.1 nm/cycle$ ), achieving 100% conformal step coverage across complex 3D topographies.

→Prerequisites & continue reading

Prerequisites: ["p07-t7.1-t1-thermal-oxidation-deal-grove-fundamentals"]

Also in Topic 7.2, ALD & High-k Metal Gate Stacks:

Tier 2 · ALD Reactor Hardware: Precursor Pulsing, Purging & C…Tier 3 · Interface Engineering, Dipole Formation & Work Funct…