Interface Engineering, Dipole Formation & Work Function Tuning in HKMG Stacks

01Interfacial Layer (IL) Engineering & Chemical Scavenging

To suppress interface states $D_{it}$, a ultra-thin, high-quality Interfacial Layer (IL) of $Si{O}_x$ or SiON (~$0.5-0.7\text{ nm}$) must be formed prior to $Hf{O}_2$ ALD.

However, this lower-k $Si{O}_x$ layer acts in series capacitance with the $Hf{O}_2$ film, capping the minimum achievable EOT:

To scale EOT below $0.6\text{ nm}$ in sub-2nm nodes, process engineers use Chemical Scavenging:

• Oxygen-scavenging metals (such as Ti, Al, or Hf metal cap layers) are deposited above the high-k stack.
• During high-temperature annealing ($900^{\circ }\text{C}$), the scavenging metal pulls oxygen atoms out of the underlying $Si{O}_x$ interfacial layer through the $Hf{O}_2$ film, thinning the IL down to $0.3\text{ nm}$ without increasing $D_{it}$.

02Work Function Metal Tuning for NMOS and PMOS

To achieve target threshold voltages ($V_{th}\approx \pm 0.2\text{ V}$) without heavy channel doping (which causes random dopant fluctuation), the effective work function (${\Phi }_{m,eff}$) of the metal gate electrode must match the conduction and valence band edges of silicon:

• NMOS Target Work Function (Band-Edge): ${\Phi }_{m,eff}\approx 4.05\text{ eV}\pm 0.1\text{ eV}$ (near Si conduction band $E_c$).
• PMOS Target Work Function (Band-Edge): ${\Phi }_{m,eff}\approx 5.17\text{ eV}\pm 0.1\text{ eV}$ (near Si valence band $E_v$).

Metal Stack Formulations:

1. NMOS Metal Gates: Aluminum-doped titanium carbide ($\text{TiAlC}$) or titanium aluminum nitride ($\text{TiAlN}$). Aluminum diffusion lowers the metal work function toward $4.05\text{ eV}$.
2. PMOS Metal Gates: Stoichiometric titanium nitride ($\text{TiN}$) or molybdenum nitride ($\text{MoN}$) with high nitrogen content, achieving work functions above $5.0\text{ eV}$.

03Interface Dipole Engineering ($L{a}_2{O}_3$ vs. $A{l}_2{O}_3$)

An alternative or complementary technique to work function metal switching is Interface Dipole Engineering:

• NMOS Dipole Cap ($L{a}_2{O}_3$ / $Y_2{O}_3$): Deposition of a sub-monolayer ($0.2\text{ nm}$) of Lanthanum Oxide at the $Hf{O}_2/{\text{SiO}}_x$ interface creates a net interfacial dipole vector pointing toward the silicon substrate, shifting the threshold voltage negatively by up to $-300\text{ mV}$.
• PMOS Dipole Cap ($A{l}_2{O}_3$): Deposition of Aluminum Oxide creates a dipole vector pointing in the opposite direction, shifting $V_{th}$ positively by $+200\text{ mV}$.

→Prerequisites & continue reading

Prerequisites: ["p07-t7.2-t2-ald-reactor-hardware-precursor-pulsing-kinematics"]

Also in Topic 7.2, ALD & High-k Metal Gate Stacks:

Tier 1 · Atomic Layer Deposition (ALD) & High-k Metal Gate (H…Tier 2 · ALD Reactor Hardware: Precursor Pulsing, Purging & C…