Silicon UniversitySEMICONDUCTOR MANUFACTURING About the project
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  1. 101 Quartzite
  2. 102 Ingot
  3. 103 Wafering
  4. 104 Pillar 6 · Plasma Etching
  5. 105 BEOL
  6. 106 Packaging

Silicon University / Pillar 06 · Plasma Etching & Atomic-Scale Material Removal / Topic 6.3 · High-Aspect-Ratio Plasma Etching

Tier 1 · Core Fundamentals 12 min read

High-Aspect-Ratio (HAR) Plasma Etching: Core Principles & Challenges

Explains the unique challenges of etching vertical features 50 to 100 times deeper than they are wide, such as 3D NAND memory holes and Through-Silicon Vias (TSVs).

Engineering StudentsFab OperationsTechnology Analysts
Dimitri AlbinoProject Leader, Advanced Wet Processing Equipment Manufacturing & Deployment

01What is High-Aspect-Ratio (HAR) Etching?

In semiconductor manufacturing, the Aspect Ratio (AR) of a feature is defined as the ratio of its depth (H) to its width or diameter (W):

While standard planar CMOS processing deals with aspect ratios of 3:1 to 10:1, modern 3D architectures, specifically 3D NAND Flash Memory and Through-Silicon Vias (TSVs), require etching vertical channels with extreme aspect ratios exceeding 80:1 to 100:1.

Process schematicSchematic · source diagram
CONVENTIONAL ETCH (AR ~ 5:1)HIGH-ASPECT-RATIO ETCH (AR ~ 80:1)W = 100nmW = 100nmH = 500nmH8000nm (8 microns)

02Primary Industrial Applications: 3D NAND & TSVs

  1. 3D NAND Channel Hole Etch: Modern 3D NAND flash devices stack over 200 to 300 alternating layers of silicon oxide () and silicon nitride () ONON memory stacks. A single plasma etch step must pierce through this thick stack to punch uniform wide memory channel holes from top to bottom.
  2. Through-Silicon Vias (TSV): In 2.5D/3D heterogeneous packaging, TSVs require etching deep vertical silicon vias ( wide by deep, ) to establish vertical electrical interconnections across stacked memory and logic dies.
Figure 1
FIG. 1

03Fundamental Physical Obstacles in Deep Trenches

As a trench deepens, the plasma etch process experiences severe physical transport limitations:

Physical Limitations In Har TrenchesSchematic · source diagram

PHYSICAL LIMITATIONS IN HAR TRENCHES

1. Neutral Radical Depletion (Knudsen Diffusion Limit)

2. Ion Angular Dispersion & Sidewall Charging Deflection

3. Reaction Byproduct Transport Blockade (Clogging)

  • Knudsen Diffusion Resistance: At deep trench bottoms, gas molecules collide more frequently with trench walls than with each other, reducing neutral radical arrival flux by over .
  • Sidewall Charging & Ion Deflection: Insulating oxide/nitride sidewalls accumulate positive charge from incoming ions, creating electrostatic repulsion that deflects subsequent ions into sidewalls, causing bowing and twisting.
  • Byproduct Redeposition: Heavy non-volatile fluorocarbon etch byproducts become trapped at trench bottoms, blocking further chemical removal.
Figure 2
FIG. 2
Figure 3
FIG. 3

→Prerequisites & continue reading

Prerequisites: ["p06-t6.1-t1-plasma-etching-rie-icp-ccp-fundamentals"]

Also in Topic 6.3, High-Aspect-Ratio Plasma Etching:

Tier 2 · HAR Etcher Hardware: Cryogenic Sub-Zero Cooling & Hi…Tier 3 · Deep-Trench Ion Transport, ARDE Modeling, Striation …